Design of Application Software for Embedded Signal Processing

High Performance Computing (HPC) technology is being used to provide scalable and cost-eeective solutions to many Embedded Signal Processing (ESP) applications. Such applications are computationally intensive and require real-time performance. To meet such requirements, algorithmic techniques are needed to eeectively utilize available HPC platforms. In this paper, we address the design issues in performing embedded signal processing applications on HPC platforms. The computational characteristics of ESP applications are rst identiied. Then, state-of-the-art HPC technology is brieey reviewed. Based on the features of the ESP applications and those of the HPC platforms, we identify the key issues in designing ESP application software. We deene a task model to capture the features of ESP applications. Various design problems are deened using this model. Then, we address the issues in developing scalable and portable algorithms for these applications. The algorithmic issues are illustrated using our task mapping methodology. This methodology is developed based on our execution model using a novel technique called stage partitioning. There are three steps in the task mapping methodology: data remapping, coarse resource allocation, and ne performance tuning. Using this methodology, a case study shows parallelizing an adaptive sonar beamformer on an IBM SP-2.